1. Field of the Invention
The present invention relates to a method of fabricating a flash memory, and more particularly, to a method of fabricating a flash memory which can perform both erasing and programming by the Fowler-Nordheim tunneling effect.
2. Description of the Related Art
The gate of a conventional flash memory comprises a floating gate for charge storage and a control gate for data accessing. The floating gate is in a floating state without being connected to any electrical circuit and is located between the control gate and a substrate. The control gate is connected to a word line. FIG. 1 schematically shows an equivalent circuit diagram according to the prior art. In FIG. 1, WL.sub.1 and WL.sub.2 are word lines, and BL.sub.1, BL.sub.2, BL.sub.3 and BL.sub.4 are bit lines. This is an arrangement that can achieve a higher integration density currently. The operation of the arrangement is to program from a drain region in a fashion of channel hot electron injection (CHEI) and to erase from a source region in a Fowler-Nordheim (FN) tunneling fashion. However, the CHEI needs a higher voltage to operate; it thus consumes more energy. Furthermore, with respect to programming speed, the CHEI operation is faster than the FN tunneling operation, but the CHEI operation may shorten the lifetime of a flash memory cell. Thus, the overall performance of a flash memory cell that both programs and erases by the FN tunneling operation is better than that of a flash memory cell that separately programs by a CHEI operation and erases by a FN tunneling operation.
In a conventional method for fabricating a flash memory as shown in FIG. 1, an oxide layer is formed on a substrate by thermal oxidation, and a bar-shaped first polysilicon layer is formed thereon. A dielectric layer and a second polysilicon layer are formed over the substrate. Subsequently, the second polysilicon layer, the dielectric layer and the bar-shaped polysilicon layer are patterned to form a bar-shaped control gate made of the second polysilicon layer perpendicular to the bar-shaped first polysilicon layer before being patterned which has been patterned to into multiple floating gates. Since the thickness of the tunneling oxide layer between the floating gate and the substrate is uniform, it is not suitable for programming and erasing by a FN tunneling operation. This is because adjacent memory cells affect each other in FN tunneling operations and the bit-by-bit definition cannot be performed. Therefore, if the FN tunneling operation is used to program and to erase for the device design, then such arrangement of cell memories having a high integration density cannot be adopted.